Among conventional non-volatile semiconductor memory devices, there are ones in which each data bit is held by two non-volatile memory elements for storing data having a complementary logic relationship, a differential sense amplifier is used for read operations, and its inputs IN+and IN− respectively receive the potentials at data lines (Conventional Example 1; refer to Patent Document 1). By employing such a structure, it becomes possible to read data reliably even when a difference between the threshold voltages of the two non-volatile memory elements is small, and since a small potential difference can be detected, it becomes possible to read data of a pair of non-volatile memory elements having a small difference in the threshold value between a depletion state, in which data writing depth is shallow, and an enhancement state.
Further, among conventional non-volatile semiconductor memory devices, a non-volatile semiconductor memory device shown in FIGS. 6 to 8 is known (Conventional Example 2). The non-volatile semiconductor memory device relating to Conventional Example 2 comprises first diffusion regions 107, select gates 103, second diffusion regions (121 in FIG. 6), floating gates 106, and control gates 111 in a memory cell array (refer to FIGS. 6 and 7).
The first diffusion regions 107 extend in one direction on the surface of a substrate 101. They are disposed in parallel and separated from each other. The first diffusion regions 107 are used as local bit lines (LB in FIG. 8). The select gates 103 are provided in a region between the juxtaposed first diffusion regions 107 and on the substrate 101 with an insulating film 102 interposed in between. They extend in the direction in which the first diffusion regions 107 extend. The second diffusion regions (121 in FIG. 6) are provided outside the cell region on the surface of the substrate 101 and underneath the select gates 103. On both sides outside the cell region, they extend in the direction perpendicular to the direction in which the select gates 103 extend. The second diffusion regions (121 in FIG. 6) are used as common sources. The floating gates 106 are memory nodes and are provided in a region between the first diffusion regions 107 and the select gates 103 with the insulating film 102 interposed in between. Viewed from a direction, normal to plane (termed as “plane direction”, herein after) they are provided insularly. The control gates 111 are provided on the top of the floating gates 106 and the select gates 103 with an insulating film 108 interposed in between. They are disposed in parallel and separated from each other, and extend in the direction perpendicular to the direction in which the select gates 103 extend. The control gates 111 are used as word lines (W0 to W15 in FIG. 8).
One of the first diffusion regions 107 disposed on both sides of the select gate 103, the floating gate 106, the control gate 111, and the select gate 103 constitute a first unit cell, and the other first diffusion region 107 out of the first diffusion regions 107 disposed on both sides of the select gate 103, the floating gate 106, the control gate 111, and the select gate 103 constitute a second unit cell. The first unit cell and the second unit cell share a channel underneath the select gates 103. In this non-volatile semiconductor memory device, an inversion layer 120 is formed in the cell region underneath the select gate 103 and on the surface of the substrate 101 by applying a positive voltage to the select gates 103.
Referring to FIG. 8, the local bit lines LB are electrically connected to global bit lines GB via selection switches SW. Each global bit line is electrically connected to a corresponding sense amplifier SA. The sense amplifiers SA amplify potential differences between the global bit lines GB and a reference global bit line RGB. The reference global bit line RGB is electrically connected to each of the sense amplifiers SA.
The operation of the non-volatile semiconductor memory device relating to Conventional Example 2 will be described with reference to the drawings. FIG. 9 is a schematic diagram for explaining the read operation (when electrons are not accumulated (changed) in the floating gate) of the semiconductor memory device relating to Conventional Example 2.
In a read operation, the first unit cell or the second unit cell is selected and read. Referring to FIG. 9, in a state in which electrons are not accumulated in the floating gate 106 (erased state; low threshold voltage), electrons e run from the first diffusion region 107 through a channel underneath the floating gate 106, further run through the inversion layer 120 formed underneath the select gate 103, and move to the second diffusion region (121 in FIG. 6) when a positive voltage is applied to the control gate 111, the select gate 103, and the second diffusion region (121 in FIG. 6). On the other hand, in a state in which electrons are accumulated in the floating gate 106 (written state; high threshold voltage), even when a positive voltage is applied to the control gate 111, the select gate 103, and the second diffusion region (121 in FIG. 6), the electrons e do not flow because there is no channel underneath the floating gate 106 (not shown in the drawing). The read operation is performed by interpreting data (0/1) based on whether or not the electrons e flow.
Compared to the non-volatile semiconductor memory device relating to Conventional Example 1, the non-volatile semiconductor memory device relating to Conventional Example 2 is structured such that it reads the object storage node of an independent unit cell facing the non-object storage node with the select gate 103 interposed in between by having the channel of the select gate 103 serving as the drain and performing a read operation without going through the non-object storage node of the other unit cell, and since it practically functions as a 1-bit cell, the chip size and chip cost can be reduced and stable circuit operation can be achieved.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2002-237191A, whose entire disclosure is incorporated herein by reference thereto.